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1/24 AN1673 application note april 2004 introduction because of the much high efficiency that can be achieved (higher than the traditional pwm) and the re- duction of the high frequency electromagnetic interference (thanks to the utilization of parasitic parameters of the circuit), the interest for resonant topologies is recently growing in power conversion market. in fact this kind of topologies allows high power/weight ratio and low power dissipation of the power parts. several power supply application segments such as adapters, television, monitor, telecom and car ra- dio can benefit by using converters based on the topology. the l6598 is designed for half bridge configuration. this paper deals on how to use this device. at the end, it will be discussed concerning some design criteria and application tips. featured device description the device, whose internal block diagram is shown in fig.1, is an integrated circuit realized in off-line tech- nology. able to drive powermos or igbt, in half bridge topology, it is provided with all the features (such as vco, soft-start, op-amp and enables) needed to implement and control properly a resonant smps with the minimum components count. even though the device is able to withstand high voltage, it can operate at low voltage starting from its operative supply. it is available in dip16 and so16n packages. the most significant peculiarities are: ? high voltage rail (up to 600v) and immunity ( 50 v/ns) at full temperature range. ? 250 ma (source) / 450 ma (sink) driver current capability. ? under voltage lockout. ? precise current controlled oscillator and frequency shift for soft-star function. ? integrated bootstrap driver for c-boot charging. figure 1. internal block diagram dv dt ------ vref ifmin ifstart op amp 12 vs c fil cf opout opin- opin+ rfmin rfstart 5 6 7 4 2 3 hvg out lvg gnd en1 en2 c ss 1 9 8 10 11 v s 14 15 16 vthe1 lvg driver vthe2 vboot cboot h.v. bus load vref vco i ss uv detection hvg driver level shifter + + - + - - dead time driving logic control logic bootstrap driver d03in1429 l6598 off-line controller for resonant converters
AN1673 application note 2/24 device pins function pin # name description 1c ss soft start timing capacitor. the device is provided with soft start features. the capacitor c ss sets the soft start time, according to the relations: t ss = k ss c ss (typ. k ss = 0.15 s/ f). in steady state the voltage at pin1 is 5v. during t ss a current iss, function of ifstart, charges the capacitor. anyway t ss , set at k ss c ss depends only on c ss value. see pin-2 and timing description in the data-sheet. 2r fstart maximum oscillation frequency setting. a resistance connected between this pin and ground sets the f start value, fixing the difference between f start and f min (f start > f min ). the voltage at this pin is fixed at v ref = 2v, so r fstart programs the i fstart current = v ref /r fstart . the r fstart value is recommended to be not less than 18 - 20 kohm. 3c f oscillator frequency setting. the c f capacitor, with r fstart and r fmin , sets f start and f min . in normal operation this pin shows a triangular wave. see timing and oscillator section in the data- sheet. 4r fmin minimum oscillation frequency setting. a resistance connected between this pin and ground sets the f min value. the voltage at this pin is fixed at v ref =2v, so r fmin sets the ifmin current equal to v ref /r fmin . to set precise frequency, the r fmin value is recommended not to be less than 20 kohm. 5op out out of the operational amplifier. characterized with 1m-gain bandwidth product, this op amp is a free feature for any need. to implement a feedback control loop this pin can be connected to the r emind pin by means of an appropriate circuitry. 6op in- inverting input of the operational amplifier. 7op in+ non inverting input of the operational amplifier. 8 en1 enable 1. this pin forces the device in latched shutdown state (the same as in under voltage conditions). active high, the typical threshold level is 0.6v. there are two ways to resume normal operation. the first is to reduce the supply voltage below the under voltage threshold and then increase it again until the valid supply is recognized. the second is activating en2 input. the enable-1 is especially designed for strong fault (e.g. in case of short circuit or open load). 9 en2 enable 2. enable input (active high at 1.2v threshold level). when activated, this function forces the soft-start sequence to be executed. the en2 is prevalent on en1 and so; it is possible to cancel the latched enable (en1). 10 gnd ground 11 lvg low side driver output. this pin must be connected to the low side power mosfet gate of the half bridge. a resistor connected between this pin and the power mos gate can be used to reduce the peak current. 12 v s supply voltage. this pin will be connected to the supply filter capacitor. an internal clamp (15.6v typical) limits the supply voltage. 13 n.c. not connected. this pin is not internally connected thus increasing the distance between the high voltage and low voltage circuitry. the increased distance gives benefit for insulation. 14 out high side driver floating reference. this pin must be connected close to the source of the high side power mos or igbt. 15 hvg high side driver output. this pin must be connected to the high side power mosfet gate of the half bridge. a resistor connected between this pin and the power mos gate can be used to reduce the peak current. 16 v boot bootstrapped supply voltage. the bootstrap capacitor must be connected between this pin and v s . a patented integrated circuitry replaces the high voltage external diode. this feature is achieved by means of a high voltage dmos, synchronously driven with the low side power mosfet. see bootstrap section in the data-sheet for details.
3/24 AN1673 application note device operation. the device will start its function as the supply voltage reaches the uvlo threshold. before the supply threshold is o.k., both the external half bridge's powermos are cut off thank to the low impedance of the drivers. as the supply is valid, the circuit starts to run; the low side driver is active during the first half period so that the boost capacitor will be fully charged. the oscillator is based on a current controlled oscillator. choosing the appropriate biasing at r fmin and r fstart we can define the minimum and maximum frequency operation limits. the device is provided with soft start function (ss); connecting a delay capacitor at c ss , it can be controlled ss time. at start up the frequency is set to the maximum value (fmax) and will gradually decrease to the operative one during the startup time. the oscillator controls the power stage circuit by the low and high side gate drivers, connected to the external power mos . the control of the frequency can be done acting on the r fmin in closed loop con- trolled condition. the significant current capability of both, the high and low side drivers (typically 450ma source and 250ma sink), allows many different power mos size to be driven maintaining fast switching transition. the internal logic ensures a dead time between the gate turn off of the high/low side and the low/high side gate turn on. this important feature allows to easily operating in zero voltage-switching mode, minimizing the tran- sistor switching losses and the electromagnetic interference (see below in the soft switching section). the built-in dead time is typical 300ns; the transition will be completed within this time. the integrated bootstrap function, allows avoiding the need of the external fast diode for charge the boot- strap capacitor (required to supply the floating driver). the internal operational amplifier can be useful in closed loop control or protection function. soft start and oscillator. the soft start function consists in a period of time, t ss , in which the switching frequency shifts from fstart to f min . this feature is detailed explained below (ref. to fig.2). figure 2. soft start timing and oscillator to drivers phase. during the soft start time the current i ss charges the capacitor c ss , generating a voltage ramp which is delivered to a trans conductive amplifier, as shown in fig. 2. thus this voltage signal is converted in a grow- ing current, which is subtracted to i fstart . therefore the current, which drives the oscillator to set the fre- quency during the soft start, is equal to: [1] v s t ss f start f min v css f out d03in1441 lvg hvg c f i osc i? min i? start gm v ccs t () ? ? () + i? min i? start gm i ss ? c ss --------------------- - t ? ?? ?? ?? + ==
AN1673 application note 4/24 where: [2] at the start-up (t=0) the l6598 oscillates (see also fig3 and relation [7]) at f start : [3] set by: [3b] at the end of soft start (t = t ss ) the second term of eq.1 decreases to zero and the switching frequency is set only by i min (i.e. r? min ): [4] since the second term of eq.1 is equal to zero, we have: [5] note: there is not a fixed threshold of the voltage on c ss in which the soft start finishes (i.e. the end of the frequency shifting), and t ss depends on c ss , i? start , gm, and i ss (eq. 5). making t ss independent of i? start , the i ss current has been designed to be a fraction of i?s tart , so: [6] in this way the soft_start time depends only on the capacitor c ss . the typical value of the k ss constant (soft start timing constant) is 0.15 s/ f . the current i osc is fed to the oscillator as shown in fig. 3. it is twice mirrored (x4 and x8) generating the triangular wave on the oscillator capacitor c f . referring to the internal structure of the oscillator (fig.3): [7] where: i osc = 4 ir? min ; ? v c is the peak to valley oscillator value ( 2.84v). a good relationship to compute an approximate value of the oscillator frequency in normal operation is: [7b] the degree of approximation depends on the frequency value, but it remains much good in the range from 30khz to 100khz (fig.4). i? min vref r? min ---------------- - ; i? start vref r? start ------------------ - ; vref = 2v == ? start 1 t -- - i osc 2c? v c ? ? ? ------------------------------- == iosc0 i? min i? start + vref 1 r? min ---------------- 1 r? start ------------------ - + ?? ?? == i osc t ss () i? min vref r? min ---------------- - == i? start g m i ss ? c ss -------------------- t ss ? ? 0t ss ? c ss i? start ? g m i ss ? -------------------------------- == i ss i? start k ---------------- t ss ? c ss i? start ? g m i ss ? -------------------------------- t ss ? c ss g m k ? --------------- - t ss ? k ss c ss ? == == ? min 1 t -- - 2 i osc c? v c ? ? ----------------------- - == ? min 1.41 r? min c? t ? ------------------------------ - =
5/24 AN1673 application note figure 3. oscillator block figure 4. frequency diagrams bootstrap section. the supply of the high voltage section is obtained by means of a bootstrap circuitry. this solution normally requires a high voltage fast recovery diode for charging the bootstrap capacitor (fig. 5a). in the device a patented integrated structure, replaces this external diode. it is realised by means of a high voltage dmos, driven synchronously with the low side driver (lvg), with in series a diode, as shown in fig. 5b. + t ss c ss c f i ss i fstart i fmin i osc s r v th+ v th- + + x4 x8 d03in1444 0 0 200 400 cf(pf) 200 400 fmin (khz) rf=90k ? - calc. rf=90k ? - meas. rf=19.9k ? - calc. rf=19.9k ? - meas. d03in1442 20 40 60 80 100 r fmin (k ? ) 20 40 60 80 100 f min (khz) d98in891
AN1673 application note 6/24 figure 5. bootstrap driver. to drive the synchronised dmos it is necessary a voltage higher than the supply voltage v s . this voltage is obtained by means of an internal charge pump. the diode connected in series to the dmos has been added to avoid undesirable turn on of it. the intro- duction of the diode prevents any current can flow from the v boot pin to the v s one in case that the supply is quickly turned off when the internal capacitor of the pump is not fully discharged. the bootstrap driver introduces a voltage drop during the recharging time of the capacitor c boot (when the low side driver is on), which increases with the frequency and with the size of the external power mos. it is the sum of the drop across the r dson and of the diode threshold voltage. at low frequency this drop is very small and can be neglected. anyway increasing the frequency it must be taken in to account. in fact the drop, reducing the amplitude of the driving signal, can significantly increase the r dson of the external power mos (and so the dissipation). to be considered that in resonant power supplies the current, which flows in the power, mos decreases increasing the switching frequency and generally the increases of r dson are not a problem because pow- er dissipation is negligible. the following equation is useful to compute the drop on the bootstrap driver: [8] where q g is the gate charge of the external power mos, rd son is the on resistance of the bootstrap dmos, and t charge is the time in which the bootstrap driver remains on (about the semi period of the switching frequency minus the dead time). the typical resistance value of the bootstrap dmos is 150 ohm. for example using a power mos with a total gate charge of 30nc the drop on the bootstrap driver is about 2.5v, at a switching frequency of 200khz. in fact: [9] in practice, if a significant drop on the bootstrap driver (at high switching frequency when large power mos are used) represents a problem, an external diode can be used, avoiding the voltage reduction on the c boot . v s v s v boot d boot ab v out v boot v out c boot c boot lvg d02in1390 v drop i ch e arg r dson v diod v drop q g t ch e arg ------------------- - r dson v diode + ?? ? + ? = v drop 130nq 2.3 s ------------------ 150 ? 0.6v 2.6v ? + ? =
7/24 AN1673 application note enable functions. the l6598 is provided with two different enable inputs, en1 (pin8) and en2 (pin 9), suitable for a flexible control of the application. the enable 1 (active high) threshold is typically 0.6v. when activated, it forces the device in a latched shut down state in which the oscillator is stopped and both hvg and lvg are cut off, like in the under voltage condition. in this state the device sinks from the supply a low quiescent current (250 a max.). there are two ways to restart the device: one is reducing the supply voltage below the turn off threshold (then turning it on again). the second is activating enable 2 input (fig.6). latched o.v.p function can be achieved using this function. figure 6. enable 1 timing diagrams the en2, active high, has a typical threshold of 1.2v. it restarts the start up sequence and, if the en1 has been previously activated, it resumes from the latched condition (fig.7). figure 7. enable 2 timing diagrams en1 en2 lvg hvg d98in890 v s t ss f start f min en2 v css f out t ss d03in1443
AN1673 application note 8/24 resonant applications. in the switched mode power conversion, the resonant converters can be distinguished from the non-res- onant ones observing the waveforms, specifically seen by the power switches and parasitic elements with- in the converter. in practice, in contrast to a traditional pwm (typically rectangular/trapezoidal shaped), the resonant converters waveforms contain pieces of sinusoidal ringing waveforms. the resonant conversion technique can be applied for all the converter topologies (buck, boost, flay-back). it is possible to classify this kind of converters in different classes: ? series or parallel load of the resonant circuit. ? fixed or variable frequency operation. ? continuous or discontinuous resonance. ? full resonant , half resonant (resonant switches) converters. this technical paper can't discuss about the variety of many different topologies. we can define resonant the converters that takes advantage of the l-c network resonance and the con- cerning possibility to switching in zero-voltage or zero-current condition. zero voltage switching is generally considered essential in high frequency-high voltage applications be- cause of the parasitic capacitors of the power devices. the zvs topology can suffer from high voltage stresses related to the ringing switch voltage wave-form, but the recent efficient way to realize the half bridge connection of the power switches, offers the soft switching features in both, "on" and "off" edges off commutation and so, the full resonant converters to be easy realized. the device is designed for the applications based on half-bridge topology, working with 50% duty cycle at variable frequency. in this type of converters the control of the output parameters will be accomplished by varying the switching frequency. the most popular load resonant converters (sr series resonant, pr parallel resonant, lcl type series resonant and so on) can be implemented using this configuration (see fig. 8). figure 8. half bridge connection. in the present discussion (for highest interest on it), we will normally refer to applications realized by using a transformer (t) in charge of to separate the load from the mains. moreover, because of the device operation mode, the continuous mode resonant converter is the config- uration of our interest (ref fig.9). in particular, we will refer to the lcl. l-series l-magnetizing cres q h driver-h driver-l q l dh load v@cres v@out time time +hv-bus dl out d03in1434
9/24 AN1673 application note figure 9. insulated lcl converter resonant circuits. any resonant circuit includes capacitors and inductors. since we deal about applications using the trans- former, it can be useful to recall the equivalent scheme of the transformer (fig.10), with its simplification and parameters. the stray inductance is the one that can be measured from the primary side with the secondary winding in short circuit connection. the magnetizing inductance is the one that can be measured from the primary opening the secondary. the parasitic capacitors will not be considered. the simplified diagram of the transformer is acceptable for the present circuits discussion. figure 10. transformer equivalent circuit we can now define some basic resonance circuits and their inherent impact on the application, (ref. to fig.11). l-series transformer boot +hv-bus hvg out lvg c-boot qh ql dh rect cfilt cres load dl c.m.s.r.c. driver-h driver-l l6598 gnd d03in1435 l/1-stray primary l/2-stray secondary cstray1 cstray1-2 d03in1430 l.magnetizing lstray l.magnetizing transformer equivalent circuit diagram simplified transformer diagram load load
AN1673 application note 10/24 figure 11. resonance's lcl-resonant converter in the diagram at fig.11, it can be observed the net circuit (seen from the out node) driven by the half bridge totem pole. the circuit path consists in the series of a determine inductors (l_ res1 ), the primary of the transformer (l mag. // load) and the resonant capacitor (c res ). we call the series of the l_ res1 and the magnetizing inductance (l mag. ) l_ res2 . the c os , placed between out and ground, is the equivalent capacitance seen at the driving node (related to the power switches and to the circuit's distributed capacitors). let's start calling basic resonance the one concerning the circuit path net c os + l_ res + c res . where l_ res can range between l_ res1 and l_ res2 depending on the load value. assuming the c res (tens or hundreds nf) value much higher than the c os one (c os is normally in the range of nf or lower values), we can just consider the series c os + l_ res . this basic resonance concerns the soft switching operation. soft switching. still referring to figure 10: the external active switch (q h ) is cut off before the current across the induc- tance reaches its zero (the active time is less than half period), the current is so forced to flow from the node out; initially discharging c os then, as the voltage cross the voltage threshold, throw the free wheel- ing diode d l . after a short time ( 300ns), when the drain-source voltage of q l is close to zero, the inherent gate driver will be activated confirming its "on" state. the same will arises at the second half period: driving off the active ql produces the commutation of the node out thanks to the energy transferred from the coil l _res to the capacitance cox and the resulting activation of the opposite diode dh. both the rising and falling edges of the commutation can be considered as portions of the "above defined basic resonance. in fig.12 it can be observed the portion of sine shaped of the out node commutations. lext lstray lmagn driver-h load out qh +hv-bus h.b. resonances dh l-res1 l-res2 dl c os cres ql driver-l d03in1431
11/24 AN1673 application note figure 12. soft switching this way to operate allows the "zero-voltage switching" thus dramatically reducing the switching losses and improving the noise immunity of the system. to operate in soft switching, it has to be ensured that the gate cut-off is forced before the current, flowing in the load, reaches the zero or its polarity is reversed. as can be easy realized, care will be taken in order to do not disconnect the out node. the basic resonance and its consistent soft switching operation, is essential for resonant converters even if it is not involved in the energy regulation. varying the frequency for the regulation. as the soft switching condition can be ensured, let us proceed describing the resonant circuitry that allows controlling the output by varying the switching frequency. the resonant path is inherent to the circuit l_ res + l- magnetizing //l oad + c res (see fig. 13) and its resonance is applicable to modulate the energy transferred to the output (load), varying the frequency. figure 13. lcl resonant path the load block (connected in parallel to the magnetizing inductor) includes the load "seen at the second- ary" reflected back to the primary. now, we must consider that the load could vary much (the extreme limits are the short circuit and the open load). moreover, in the real converter (see fig14), the load includes a rectifier section and the output filter. therefore, even in the limits of the single cycle, the load changes much and the l-m agnetizing can be seen in parallel to a very low impedance during the diode conduction (charging co) and to very high im- pedance as the diode is cut off (i.e. as the instantaneous voltage at the anode drops down lower than the output one). 100nsec/div. 0 200 400 600 v out (v) d03in1445 l-magnetizing l-series load cres d03in1432
AN1673 application note 12/24 figure 14. simplified real converter consistent with the above consideration, we can see the circuit as a multiple resonant path. e.g. in the family of curves depicted in fig.15, it can be observed the trend of the admittance as a function of the frequency, for different resistive load. figure 15. multiple resonance we have two separate peak of resonance: the first peak (f01, lower in frequency) is inherent to the magnetizing inductance (in series with the l.ext. if one is connected) it is the case with the load open. the second resonance (f02) depends on the series inductance l_ series (case in which the load is much heavy or during the rectifier's conduction phase). both the resonance play a role in the energy transferred to the load and its control. we can start to discuss assuming the value of the magnetizing inductance (l-m agnetizing ) is so high that its current is negligible for the frequency range of our interest. in this hypothesis, it is evident that the maximum current will occurs at the peak of f02 resonance; it should not be reasonable to operate at frequency lower than f02 in order do not loosing the zero-voltage switch- ing and also because the energy transferred to the load should not longer be increased reducing the fre- quency. in the practice, for the real transformer, the magnetizing inductance can't be negligible (its value will not be so high). anyway it should be possible to control its value making so it possible to operate at switching frequency lower than the f02 (see fig16). secondary side primary side transformer c res l-ser h s l s h v bus full bridge rectification n2 n1 c o load v out d03in1433 1-10 4 1-10 5 1-10 6 z 1 log d03in1446 f01 f02 operating locus ()
13/24 AN1673 application note figure 16. v out + i (cres) characteristics. the control of magnetizing inductance (in the lcl topology) can play an important role in the energy man- agement; its value (and its ratio with l- series ) will affect more than one behavior of the application. assuming the load is disconnected, the maximum current occurs at the peak of f01 resonance that con- cerns the path l magnetizing + c res . the value of the magnetizing inductance will be (usually) significantly higher than the series inductance, consistently; the "lowest" resonance (f01) is mainly dependant on its values. we can define f01 "lowest" resonance to well remind that the switching frequency must not be lower than its value. in fact, forcing the half bridge working at lower frequency (f01), the series circuit represents a capacitive load. this condition cannot be accepted in the application for the following reasons: ? in capacitive load the "zero voltage switch operation" is lost with resulting significant power dissipation (hard switching). ? in closed loop, the transfer function should be reversed (when going in below resonance) and the con- trol should be lost. to summarize: it is needed to operate in the "inductive region" of the curve. in this way, the higher frequency applied to the resonant net, the lower is the resulting power. it is remarkable that, working in the deep inductive mode (far from the peak of resonance), the current moves from sinusoidal shape to triangular and wide frequency change is requested to control the regula- tion. on the contrary, working as close as possible to the resonance, for a given load change, the frequency variation will be minimized. if the application is designed to operate between to the "lowest" resonance (f01) and the second reso- nance (f02), it will be verified that the primary current (at the switch off time of one of the two powermos), should not be too low in order to ensure the energy needed for soft switching in all condition. the l6598 function and the resonance's effects in the regulation have been discussed. now we can start to describe some design criteria. 5 sec/div. 0 200 400 600 -1 0 1 2 (1) (1) (2) (2) v out (v) i (cres) d03in1449
AN1673 application note 14/24 design criteria and application tips. the description of design flow is referred to the implementation of the demo-board prototype used for eval- uation. the whole schematic that comes from the design process below described is shown in fig. 17. figure 17. diagram of the application r1 750k ntc f1 fuse p1 bridge r6 68k r8 47k r14 16k r22 47k r15 1.8k r9 0.82 r10 0.82 q1 stp9nb50 (to220) q2 stp4nk50 t2 d2 1n4148 d8 1n4148 stps40l40ct d3 1n4148 d10 1n4148 d1 stta106 d9 1n4148 r4 180k r50 12k r51 560k c3 0.47 f c23 0.47 f r5 180k r2 750k v cc zcd mult 3 2 15 6 6 7 2 58 12 8 1 7 1 ra 33 r38 22 r39 100 r21 330 r7 33 resonant ac-dc adp. io=3.8a/vo=18v t1 boost inductor spec. l = 1.2mh > primar.=120turns, sec. = 12 turns 1.2mmgap. t2 center tapped transformer spec. core=e 30*15*7 coreset; 0.33mm gap twice slotted former. primary winding = 60 turns # 2 0 // 0.1mm each secondary. = 5+5 turns # 60 // 0.1mm each. aux. = 5 turns # 0.1mm.. lprim. = 0.85mh; lstray = 240uh. d13 1n4148 d12 1n4148 1n4148 l1 l1=1 h 5t prim=65 turns 5+5 turns r47 14k r48 2.2k r42 120k r44 10k vout r43 5.1k r45 4.7k r36 4.7k r40 10k r37 2.2k r33 470 r41 10k r20 22k r11 750k r12 750k r12 750k c1 680nf 400v c2 100nf c4 220nf c29 22 f c5 10 f r28 4.7k r30 4.7k c26 100nf c9 330pf c24 100nf c10 100nf to 330nf c30 8.2nf c12 100nf c12 100nf c25 2.2nf 3kv c22 100nf cx 4.7nf vcc invin1 out1 out2 invin2 niin1 vcc- vref c28 100nf c17 330pf 630v c16 22nf 630v phe428 c18 330 f 35v e30*15*7 c11 100nf dz1 15v c14 2.2 f c6 33 f 450v c13 4.7nf r3 10k gnd comp cs inv gd rf start v s en1 hvg op in- op in+ v boot out u1 l6561/2 (dip8) u2 l6598 (dip16) 16 14 7 op out cf css rf min 5 6 4 3 4 1 10 gnd 4 q3 stp4nk50 d11 1n4148 11 r23 330 r35 0.022 lvg vout 3 5 9 8 2 en2 r18 68k r46 330k c19 330 f 35v c20 100 f 35v 1n4148 r24 47k r26 12k r25 330 opto opto 5 4 1 2 6 4n35 u3 tsm103a d03in1452/mod2 c25x 4.7 f 25v
15/24 AN1673 application note for the pfc portion of the entire application, it will be dedicated a small section with a concise description and a reference for the specific application note. the following design discussion will be limited to the resonant converter. design process: the converter block diagram can be separate in some basic blocks as in fig.18. figure 18. lcl. resonant converter output rectification and filtering; transformer and resonant parts (lres-cres); half bridge; driver controls the target specification is given for 70w ac adapter, here follows the parameters and requirements: - ? output voltage vo=18v and maximum rated current controlled at io=3.8 to 4a. ? wide range mains input 85v to 264 v. ? high power factor required (p.f.c. needed); +vbus should be 360v to 420v based on these values we can start designing the output stage filter: ? the current relations at the secondary side ("contiguous sine shaped" hypothesis): [10] output filter and rectification. need to be used good quality electrolytic capacitors; the output voltage ripple is function of the equivalent series resistor (esr) (the contribution of the capacitance is negligible). set the limit to <1% using: [11] this is obtained using two capacitors (330 f with esr=75 m ? each). the power dissipated inside the ca- pacitors will results 140mw at the maximum rated output current. [12/13] the voltage ripple should around 240mv. [12] ; transf. l-mag. c res c bulk v out v in +hv bus v boot v cc out v cc drivers control l- res rectifiers d03in1458 i opk i o 2 -- - ? 6.28a; i orms i opk 2 --------- - 4.44a; i crms i orms 2 i o 2 ? 1.93a == == = = esr ? v o i opk ---------- 180mv 6.28a ------------------- 29m ? = pc o i corms 2 esr ? 140mw == ? v o esr 2 xc o + 1pk ? ? 240mv ==
AN1673 application note 16/24 the connection of a second l*c filter's cell can be much effective to limit the output voltage ripple, without exceeding a reasonable high quality capacitor number. in our case, a low price inductance (l1=1 h) and a 100 f -180 m ? esr, reduces the high frequency volt- age ripple down to 80mv (see fig.19) figure 19. output rectification and filtering because of the output current/voltage ratio, the output rectification stage can represents most of the pow- er dissipated in this kind of application. for the present application, the efficiency is significantly improved choosing the center-tapped connection; this allows to half the power dissipated on the output rectifiers. using this solution, care will be taken in winding up the secondary in order to get a good coupling between the two secondary and for a good sym- metry in the current waveforms. for our design, chose the stps40l40ct that is a low drop power schottky diode in to220ab package (v th = 0.28v ; r d = 0.0105ohm ; b v = 40v). the power dissipated on the rectifier can be estimated using the sinusoidal model: ?@ i o = 4a the peak current of secondary diode i dp = 6.3a; i rms = 4.45a; [13] p d = v th i o + r d i orms 2 p d = 1.35w ? the reverse peak-voltage of diode v o 2 36v transformer design: the lcl resonant configuration requires a resonant inductor (lser.) placed in series to the transformer's primary and to the resonant capacitor (cres.). this inductor plays an important role and its value controls the current peak during the energy-transferred phase (or in extreme heavy load conditions). since the primary path will be submitted to high frequency alternate current (with a significant large flux density swing ? b), an high quality resonant inductor should be needed in order to limit the coil's power dissipation. in much real design, the stray inductance of the transformer can efficiently replace any external resonant inductor (or minimize its value). we adopt this solution that allows saving the part and limits the magnetic power dissipation. the leakage inductance (lstray) parameter is not easy to be design and usually it requires some mechan- ical tricks for obtaining a significant value. anyway, as soon as the transformer is defined, the stray induc- tance value will be constant enough and its spread limited. apart of this, the first step is to choice the size of the magnetic set. l1 1 h t sec. da db c o1 330 f lopk c o2 330 f c o3 100 f v o d03in1459 i dp io ? 2 ------------ - = i rms i dp 2 ------- =
17/24 AN1673 application note using the "product area" (ap) criterion, we can get a first approximation of the core area product. the required ap can be found using the equations ap1 and ap2 (we use the same formulas as for the standard half bridge forward converter). ap (=aw*ae) is the winding area (aw, associated to the former) time the magnetic cross section (ae, as- sociated to the ferrite). n.b. for choosing the resonant elements (inductance and capacitor) and its relation with the frequency to be set, one can have an easy task referring to the convention described in appendix a. ? start choosing the minimum operative frequency (corresponding to full load) at 65khz. [14] ap1) # related to core losses limit where: kh = 4 10 -5 ; ke = 4 10 -10 ; ? sw = 65khz for the present design, ap1 = 0.38cm 4 [15] ap2) # related to saturation limit where: k = 0.165 related to the half bridge connection; ? bmax 0.4t; pin is the power handled by the transformer. in the present design, should be ap2 = 0.17cm 4 the needed ap will be the larger of the two resulting values. to met the current target specification, we need ap = ap1 = 0.38cm 4 . select the ferrite's set ee30 (e30 15 7) in high frequency (e.g. b2 or f1) material. (ve = 3.9cm 3 ; aw = 0.8 cm 2 ; ae = 0.6cm 2 ) => ap=aw ae=0.48 cm 4 . transformer's winding to define the winding, first it must be fixed the input dc bus value. since in the discussed design the pre regulator stage (see later in power factor section) is requested, let's start fixing the voltage bus range at 360v to 420v. the second resonant inductor of the lcl resonant converter can be achieved managing the proper value of primary inductance of transformer. this second inductance allows to properly operating in light load condition holding in the same time the higher efficiency for the entire load range. in our experience, to take advantage by using the primary in- ductance as second inductor, a good ratio between its value and the stray inductance (lmag/lstray) is in the range of 3.5 to 7. the relation between the primary and the stray inductances can be adjusted using the slotted bobbin (that increases the stray inductance) and introducing an air gap in the transformer's ferrite set (that reduces the magnetizing inductance). we choose a two layer slotted former (split the primary and secondary sides). see fig.20. figure 20. transformer ap1 41.7 pin ? k? sw ? ------------------------- ?? ?? 1.58 kh ?t ke ?t 2 ? + ? () 0.66 ? = ap2 11.1 pin ? kbmax ? ? sw ?? ------------------------------------------ - ?? ?? 1.31 = secondary slotted former primary aux. n1 prim. aux. n2a n2b t sec. d03in1460
AN1673 application note 18/24 the design of the winding starts calculating the minimum requested primary turns number. for turns number calculation: [16] ; n p 50 where: v in(min ) = 360v ; ? b = 0.230t (*) ; ae = 0.6cm 2 (*) in the case ap is defined by the ap1, ? b is calculated by the formula [17]. [17] where: ; pt = 1.3 ap1 0.37 instead, in the case that ap should by ap2, ? bmax will be fixed by the designer (up to 0.400tesla). choose primary turns number np = 60 the turn's (n = np/ns) ratio will define the secondary winding turns number. [18] ; n = 10 where: duty=0.5; choose n = 12*; secondary turns ns = 5** * the ratio n can be significantly higher than [18] because the lmag effect ** the secondary winding is realized with ns = 5+5 turns because of the center-tapped solution. in order to limit skin effect (and the inherent power losses), the litz wire solution has been adopted for the windings: ? 20 wires 0.1mm each for the primary winding (=> 0.157 mm 2 cross section) ? 60 wires 0.1mm each at the secondary winding (=> 0.47mm 2 cross section) as the primary and secondary windings have been defined, we need fix the inductances of the transformer. the formula [19] allows calculating, with good approximation, the value of the primary inductance in func- tion of ferrite set and the gap length, the ferrite's set parameters and the primary turns number. [19] where: 0 = 4 10 -7 is the absolute permeability. r is the relative permeability (e.g. 2000) le is the magnetic path length, (in cm). ae is the effective area (in cm 2 ). l_gap is the gap size (in mm). the calculated primary inductance will be in mh. in our case the l=0.85mh. n p v in min () 10 4 ? 8b ? ? sw ae ?? ? ----------------------------------------- - = b ? pcv kh ? sw ke ? sw 2 ? + ? ---------------------------------------------------- ?? ?? ?? 1 2.4 ------- - 0.230t == pcv pt 2ve ? --------------- = n v in min () duty ? v o v ? + -------------------------------------- = l 10 1 ? 0 ----------- - le r ae ? ----------------- 0.1 l_gap ? ae 0.2 l_gap 4 -- - ?? + ?? ?? 2 -------------------------------------------------------------- ? ?? ?? ?? ?? ?? ? ?? ?? ?? ?? ?? 1 ? np 2 ? =
19/24 AN1673 application note concerning the stray inductance, the models used in the standard forward application's transformers are not precise (mainly because the mechanical position). the approximate value can be foreseen using the formula: [20] in our case the calculated lleak is 270 h . where: lw = 5.6cm; bw = 0.5cm; hw = 1.55cm. in the real transformer of the present example, the stray inductance (tested at the primary when one of the secondary sections is shorted) is about 240 h. as already told, introducing an air gap in the ferrite set can control the ratio between the primary and the stray inductance. chose the air gap 0.33mm to get the ratio lm/ls=3.5, resonant capacitor (cres). for the resonant capacitor selection, it must be consider its rated current; in fact the current can be an important limit, in particular for low capacitor values. in the polypropylene series capacitor it is usually pos- sible to find the suitable one. on the other side the value of the cres, for a given resonance's value (see fig.21), profiles the sloop of the resonant curve (q factor that is function of ), thus changing the impedance change versus the frequency variations. in our design it has been chosen the 22nf/630v phe- (100c) . figure 21. q factor. powermos. concerning the powermos to be used in the half bridge, the required class of blocking voltage (bvdss) is 500v. choose stp4nb50 or the equivalent stp4nk50) the relations and parameters that can be used for calculation: [21] r in : equivalent input resistance (seen at the primary side). [22] l leak 1.3 lw np 2 ?? bw ---------------------------------- hw 3 ------- - 10 8 ? ?? lres/cres 1-10 -3 0.01 0.1 1 1-10 4 1-10 5 1-10 6 d03in1447 aa( (w)) ab( (w)) r in 8v o ? 2 i o ? -------------- - n 2 ? 818v ? 3.14 3.14 4a ?? --------------------------------------- - 144 ? 525 == = i qpk i o ? 2n ? ----------- - 4 ? 24 ---------- - 0.525 ??
AN1673 application note 20/24 where: i qpk : peak of current at the primary side #. figure 22. i (q) + i (cres) characteristics. # because the lm/ls ratio, a not negligible portion of current managed in the transformer's primary should not be transferred to the load. for this reason, using the formulas for calculate the primary side current (21& 22), the results will be significantly lower than the tested one see fig 22. bulk capacitor c-bulk. the relations for design: [23] where ? v o is the accepted voltage ripple [24] where t_hold is the requested hold-up time and v o(min) the minimum voltage for correct operating. the key points for selecting the bulk capacitor are in sequence: the rated voltage, the capacitance related to the 100hz ripple and the holdup time (on request) see also pfc documentation. choose c-bulk (6) = 33 f-450v that involve 9v voltage ripple without fixing any hold-up time. control circuits. the control of the output voltage and current has been realized with twice loop using the tsm103 (dual amplifier and voltage reference). this component, in addition to an optic coupler, allows profiling a full control of the output both of the voltage and the current profile (see fig.23). the control's parameter for the frequency variation is the current drown from r fmin (pin4). see also device operation page 3. since the control of the output could not be longer ensured in case of a heavy load (because of very low output voltage e.g.< 5v), at the primary side the current is sensed (by the c17, r26, d12+d13) and as the signal, filtered and feed to the en2 of the l6598, exceeds the threshold limit the soft start is reactivated. -1.5 t=5 s/div -1.0 -0.5 0 0.5 1.0 (a) i(qi) d03in1457 i(cres) cbulk p o 2 2? v o ? v o ?? ? ? ------------------------------------------------ - = cbulk 2p o t_hold ?? v o 2 v omin () 2 ? --------------------------------------
21/24 AN1673 application note figure 23. output v/i characteristics. miscellaneous . few critical points to be considered in design and debugging phases are: ? the frequency accuracy; the actual frequency can be affected by external components (e.g. the preci- sion of cosc. and its thermal variation). moreover, when the cosc is much low, the stray effects must be considered (the pin and pcbs capacitance). the oscillator accuracy can be affected if the current drown from the references (pin2_rfstar and pin4-rfmin) exceeds 100 a. ? the layout of pcb and coupled noises: a good criterion for checking the noises is to test the signal at the cf(pin3) that should be a symmetric triangular waveform in order to ensure the correct drivers duty. another point to be tested is the voltage at out(pin14) that, during the freewheeling, should not be too much below ground (few volt). power factor section. in spite of the pfc stage should not be strictly necessary for the resonant application, in our design it has been introduced for the following reasons. the front-end stage of conventional off-line converters, consists of a full wave rectifier bridge with a ca- pacitor filter, gets an unregulated dc bus from the ac mains. therefore the instantaneous line voltage is below the voltage on the capacitor most of the time, thus the rectifiers conduct only for a small portion of each line half-cycle. the current drawn from the mains is then a series of narrow pulses whose amplitude is 5-10 times higher than the resulting dc value. lots of drawbacks result from that: much higher peak and rms current drawn from the line, distortion of the ac line voltage, over currents in the neutral line of the three-phase systems and, after all, a poor utili- zation of the power system's energy capability. this can be measured in terms of either total harmonic distortion (thd), as norms provides for, or power factor (pf), intended as the ratio between the real power (the one transferred to the output) and the ap- parent power (rms line voltage times rms line current) drawn from the mains, which is more immediate. a traditional input stage with capacitive filter has a low pf (0.5-0.7) and a high thd (> 100%). the international norms and standard requirements have spurred the design of high power factor. for these reasons power factor corrector (pfc) is now diffusing in off-line power management. with a high power factor switching pre regulator, interposed between the input rectifier bridge and the bulk filter ca- pacitor, the power factor will be improved (up to 0.99). the current capability is increased; the bulk capac- itor peak current and the harmonic disturbances are reduced. moreover, the pfc with its pre regulated high voltage bus, provides an important advantage, because op- erating at fixed dc input, it makes much easier the resonant converter to be controlled. the l6561 is an integrated controller dedicated to pfc stage by using the transition mode technique and is optimized for low to medium power applications. 18v v_out/2 i_out 3.8a twice fback r s vo v_loop i_loop d03in1461
AN1673 application note 22/24 the pfc section of the present application has been designed to pre regulate 400v and to deliver 80w. the ac mains voltage can range from 85v to 264 v. for a detailed description of the l6561 operation, refer to an966. evaluation result. the demo board has been evaluated in two different modes. the first evaluation (see table_01) has been done for the resonant converter section (not included the pfc pre regulator circuit) at two different output power levels. in practice the resonant converter has been supplied using a 400v dc power supply and it has been eval- uated its efficiency. table 1. input supply voltage = +400 vdc the second evaluation (see table 2) has been done for the entire application circuit, including the pfc. the load has been changed as in the first evaluation (3.8a and 2a), moreover it have been set four sig- nificant values of the mains voltage according to the requested wide range. table 2a. output loaded @ 3.8a. table 2b. half load (@ 2a). pin=72w vo=17.8v io=3.8a po=67.64 n=93.9% pin=39w vo=17.8v io=2a po=35.6 n=91.3% vin=88vac pin=77.5w vo=17.8v io=3.8a po=67.64 n=87.3% vin=110vac pin=76.35w vo=17.8v io=3.8a po=67.64 n=88.6% vin=220vac pin=74.7w vo=17.8v io=3.8a po=67.64 n=90.5% vin=255 vac pin=74.4w vo=17.8v io=3.8a po=67.64 n=91% vin=88vac pin=41w vo=17.82v io=2a po=35.64 n=86.93% vin=110vac pin=40.5w vo=17.82v io=2a po=35.64 n=88% vin=220vac pin=40.3w vo=17.82v io=2a po=35.64 n=88.4% vin=255 vac pin=40.3w vo=17.82v io=2a po=35.64 n=88.4%
23/24 AN1673 application note appendix a. a practical way to handle the resonant components is to adopt the normalized voltage and current. the minimum operative frequency has been set at 65khz. this frequency can be considered a good com- promise for holding the transformer's magnetic set low size and to avoid the high frequency problems (e.g. skin effect, switching losses and so on). let us fix the normalized out put voltage m = 0.98 assume normalized operating current as j = 0.2 where: r o is characteristic impedance = the resonant zo can be calculated as z o = 120 ? the resonant capacitor will be: ? the resonant inductance references: [1] a comparison of half-bridge resonant converter topologies. robert l. steigerwald, ieee transactions on power electronics. april 1988. [2] small signal ac equivalent circuit modeling of the series resonant converter. arthur f. witulski ; robert w. erickson ieee power electronics specialist conference 1987 [3] analysis and design of lcl-type series resonant converter. by ashoka k.s. bhat, ieee transactions on industrial electronics. february 1994. [4] design optimization for an lcl-type series resonant converter m. b. borage, s.r. tiwari and s. kotaiah; power supplies division - center for advanced technology indore, india www.powerpulse.net/powerpulse/archive/aa_030501a1.stm [5] application note: an966; an1300 stmicroelectronics m v o n ? v in max () 2 ---------------------- ---------------------- ? ?? ?? ?? ?? ?? j i o r o ? n v in max () 2 ---------------------- ? ------------------------------ ? ?? ?? ?? ?? ?? lr cr ------ z o v in 2 ------- - ?? ?? 2 jm ?? v o i o ? --------------------------------- - = cr 1 z o ? -------------- - cr 1 110 2 65 10 3 ??? ---------------------------------------------- 20nf ?? ? lr z o ------ lr 110 2 65 10 3 ?? ------------------------------- - 295 h ?? ?
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